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    FPGA Verilog Programming Finalizado left

    Need help program FPGA with Artix-7 using Verliog.

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    Hardware Engineer - 08/12/2018 07:24 EST Finalizado left

    VHDL, LTE,WiMAX,Bluetooth,RF,FPGA

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    ARM firmware with LINUX for DE10-Nano board Finalizado left

    ARM firmware with LINUX for DE10-Nano board A. Play with the evaluation board 1. Project Owner will provide a P0496 ARM Processor base on Cyclone V SE FPGA computer board (DE10-Nano board). The board will have Ethernet port and SD card. 2. Developer needs to prepare LINUX Kernel to run on embedded computer board with Ethernet TCP/IP to connect with the host PC. 3. Developer needs to prove that he/she can transfer image from the SD card to the host PC. To test the feature, we will prepare a list of pictures001, pictures002, ..., pictures010 in the SD card, plug the SD card to the DE10-Nano board, press a button, a moment later the PC will has thse pictures. B. Working on the final system: 1. Project Owner will design a Cyclone V SE ARM processor base, similar to the evaluation board,...

    Android Programación en C Ingeniería eléctrica Firmware Linux
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    Urgent FPGA Verilog Project Help Finalizado left

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
    $175 (Avg Bid)
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    Zen Protocol Miner in Verilog/VHDL Finalizado left

    Implement the Zen Protocol in the FPGA and update the Mining App

    Programación en C Ingeniería FPGA Microcontrolador Verilog / VHDL
    $1220 (Avg Bid)
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    FPGA peogramming, Xillinx Finalizado left

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    Framer X designer Finalizado left

    I need a UI/UX designer to create prototypes for my website using Framer X. Let me know your experience with Framer X

    Diseño gráfico Photoshop Interfaz de usuario / AI UX / User Experience Diseño de sitios web
    $131 (Avg Bid)
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    UI/UX Designer. Finalizado left

    I need a UI/UX designer to create prototypes for my website using Framer X. Let me know your experience with Framer X

    Diseño gráfico Photoshop Interfaz de usuario / AI UX / User Experience Diseño de sitios web
    $140 (Avg Bid)
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    FPGA Designing Finalizado left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

    Ingeniería eléctrica Electrónica FPGA Verilog / VHDL
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    Project for sissoftware -- 18/12/05 17:59:44 Finalizado left

    We have an in-house trading application which we intend to move to FPGA, using metamako or solarflare fdk

    Electrónica Google Adwords Photoshop SQL Verificación / QA
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    Write 4 bit microprocessor design using VHDL and implement on Nexys 4 ddr FPGA board Finalizado left

    Its a small assignment. If you are an expert and have worked on it before. text me

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
    $138 (Avg Bid)
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    Project for TIV LAbs Finalizado left

    Hi TIV LAbs, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Have you worked on the nexys 4 ddr fpga board?

    CSS HTML PHP Diseño de sitios web WordPress
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    FPGA X13bcd miner and bitstream Finalizado left

    I am looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with reasonable performance Developer should commit to Non disclosure agreement, and is not allowed to share the code with 3rd parties without written confirmation from the project investor. Developer then send the end solution, including code base, compiled code, written documentation about how to upload the code to ( by developer specified) FPGA and how to use it, including clear written instructions how to cha...

    Arduino Programación en C Programación en C++ CUDA Microcontrolador
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    DIGITAL BLACKJACK USING BASIC!!! VHDL coding on a DE-1 Board Finalizado left

    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    Verilog / VHDL
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    Solving FPGA output module Finalizado left

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

    Arduino Electrónica FPGA Microcontrolador Verilog / VHDL
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    Solving FPGA output module Finalizado left

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

    Arduino Electrónica FPGA Microcontrolador Verilog / VHDL
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    cisco voice gateway connection to SIP server and PSTN on E1 PRI Finalizado left

    Cisco voice gateway connection to SIP server and PSTN on E1 PRI

    Asterisk PBX Cisco Linux Administración de redes VoIP
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    Building the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA Finalizado left

    Need to Build the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA

    Programación en C Electrónica FPGA Verilog / VHDL
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    Game Development Project Finalizado left

    Javascript and Phraser framer work

    CSS HTML HTML5 Java JavaScript
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    I would like to hire a Videographer Finalizado left

    Filming job in London (E1) for an accountants firm. Need approx 1 minute final footage of staff working at desks, having a meeting, moving around the office etc. Need a quote first. Final footage to be delivered in 1080 HD

    Producción de video Servicios de video Videografía
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    Rfid reading tags python Finalizado left

    We need some python software so to r...19 95 RX: 0D 00 21 00 02 44 09 03 4E 00 1E 0A F2 16 TX:04 00 21 D9 6A RX: 0D 00 21 00 02 44 09 03 4E 00 1E 0A F2 16 Set to reader device parameters reader address to 00 TX: 6(Bytes)05 00 24 00 25 29 RX: 6(Bytes) 05 00 24 00 25 29 reader power to 30 TX: 6(Bytes)05 00 2F 1E 72 34 RX: 6(Bytes) 05 00 2F 00 8D CD reader frequency 902.6~927.4 TX: 7(Bytes)06 00 22 31 80 E1 96 RX: 6(Bytes) 05 00 22 00 F5 7D reader Baud rate to 57600 TX: 6(Bytes)05 00 28 05 28 D7 RX: 6(Bytes) 05 00 28 00 85 80 reader query time to 10*100ms TX: 6(Bytes)05 00 25 0A A7 9F RX: 6(Bytes) 05 00 25 00 FD 30 Get Reader device information TX: 04 00 21 D9 6A RX: 0D 00 21 00 02 44 09 03 31 80 1E 0A A2 F2 Query tags TX: 04 00 01 DB 4B

    Arduino Linux MySQL Python Arquitectura de software
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    fpga pattern generator Finalizado left

    fpga pattern generator connected to a pc starting from an evaluation board and an HDL from TI.

    Electrónica FPGA Verilog / VHDL
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    Video Compression Using FPGA Finalizado left

    I need to perform video compression using FPGA My final aim is to get a .bit or to .bin file so that I can burn the image to my fpga and simply voila.. Kindly visit this link in order to get an insight to the board that I will be using… I want video to be input from HDMI in port on the board and output ( a compressed video) via HDMIout port on the FPGA board (Xilinx fpga and digilent atlys trainer board)

    Ingeniería eléctrica Electrónica Ingeniería Microcontrolador Verilog / VHDL
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    Looking for game source code for ios & androi Finalizado left

    I looking for source code game mobile Pls refer apk app this game

    Android iPad iPhone Desarrollo de apps móviles Objective C
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    Xilinx Vivado project ref. design Finalizado left

    I have my FPGA Xilinx Artix 7 XC7A50T development platform for my personal project. It has DDR3, Hi-speed ADC, Hi-speed DAC, UART, SPI(x2), IIC, and an Ethernet MAC. I need a complete design with microBlaze. I can provide a small example xpr prj but not yet finished. I need someone to configure and link the ip together and have it finally synthesis to a .bit file. I look for someone experienced with Xilinx Vivado 2018.1 that I use here. If you can put also Linux inside and or a small SDK application, that would be really great !

    Ingeniería eléctrica Electrónica FPGA Systems Engineering Verilog / VHDL
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    Vhdl code modifications Finalizado left

    Need a vhdl expert for Vhdl Code modification. Clock divider and counter design. Code needs to be run on an fpga. Thanks

    FPGA Verilog / VHDL
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    SD image for PYNQ on the zybo z7-20 FPGA dev board Finalizado left

    I'm trying to port PYNQ over to a diligent board that is not directly supported. I'm hoping somebody has already done this that would be willing to share their SD card files with me to save me the trouble. I'm looking for PYNQ version 2.2 or 2.3. Please and thankyou.

    FPGA Linux Python
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    Trophy icon Looking for a Data interface to PC board Finalizado left

    We have a custom imaging/camera board. It takes about 50 images at a time, with the resolution of 256x256 pixels, monochrome. We need help to find a MCU board/computer board with a H/W interface port, so we can transfer our pictures to that board, and then to PC. We do not need any help with H/W design, we need help to find the available MCU...find the available MCU/Computer board that is available on the market, such we can use, and it should need minimum S/W, firmware develops. And if you want to help more, you can help us to modify the S/W, firmware to make the system work perfect (another contract). Please refer to the block diagram in the document attached. The H/W interface with our camera is open for now, since it will be from a FPGA, and we can make it interface to any ki...

    Ingeniería eléctrica Electrónica Firmware Microcontrolador Arquitectura de software
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    Fault Tree Equation Calculator Finalizado left

    An application with an interface for user to calculate the output of supplied events. T = Issue E1,E2, En ....is the event A, B,.... is the cause user should be given a choice to provide event, cause. For every event, it need can and must have have 2 input, which can be cause or event. when it is a event, then user will be prompt for 2 inputs, since the logic cannot stop at events. Then calculate what is T by applying 1st distrubutive law, 2nd idempotent law and last absorption

    .NET Programación en C# Programación en C++ Java VB.NET
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    Verilog FPGA DE2 SO1 Board GameOver & Win Screen Finalizado left

    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

    Electrónica FPGA Microcontrolador Verilog / VHDL
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    ProjectDone Finalizado left

    The project is over VHDL using Vivado software, and it contains five smaller parts. have a fun with FPGA and hardware language.

    Programación en C FPGA LabVIEW Microcontrolador Verilog / VHDL
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    abiramiamanm Finalizado left

    vlsi coding using QUARTUS II software FPGA

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    FPGA SATA-to-SATA bridge SATA III Finalizado left

    We are looking for an implementation of a FPGA SATA-to-SATA bridge. Design should be made in VHDL and be compatible to Xilinx Aritx-7 Series. The FPGA should receive SATA as a device (SATA device controller) and forward these information after processing to one or two SATA devices as SATA host (SATA host Controller).

    Programación en C Electrónica FPGA Microcontrolador Verilog / VHDL
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    Digital To Analoge Finalizado left

    We are a Australian based company in development of Electronics, to run Piazo Printhead. I am looking for a engineer with experience in sending Digital Data to a DAC setup and amplified via Mosfets. Digital Data will be implemented on a Xilinx FPGA. Trapezoidal waveform needs to be written in VHDL so that circuit and Code simulation can be done in Tina software. An explanation of the VHDL code to be supplied so that code can be changed at any time in the future.

    Ingeniería eléctrica Electrónica Ingeniería Microcontrolador Verilog / VHDL
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    Calculator for 4x4 keypad in VHDL Finalizado left

    Develope script in XILINX ISE FPGA using nexys 4 ddr card Language VHDL For calculator

    Electrónica FPGA LabVIEW Microcontrolador Verilog / VHDL
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    Update Miner for FPGA Finalizado left

    Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA

    Programación en C Programación en C++ FPGA Microcontrolador Verilog / VHDL
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    We are Hiring Good Programmer in FPGA, GPU, CUDA, MATLAB Finalizado left

    We are Hiring Good Programmer in FPGA, GPU, CUDA, MATLAB for our Company. (Removed by Freelancer.com Admin)

    Programación en C Ingeniería eléctrica Electrónica Mathlab y Mathematica Verilog / VHDL
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    I need a coder that is proficient in VHDL coding and Usage of FPGA board(BASYS3) Finalizado left

    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    develop a CAD tool that can read in the “logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit Finalizado left

    You will develop a CAD tool that can read in the “logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created ...“logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minim...

    Programación en C Programación en C++ CAD/CAM FPGA
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    Develop a CAD tool for RAM mapper Finalizado left

    You will develop a CAD tool that can read in the “logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created ...“logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minim...

    Algoritmos Programación en C Programación en C++ CAD/CAM FPGA
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    Trophy icon Design Flyer in 24 hrs Finalizado left

    I need a flyer designed in 24 hrs please ensure its of a nice size to post on social media especially instagram. details to include: Saturday 10th November 2018 at Track & Records 94 Middlesex St, London E1 7EZ Music Policy: RnB, Hip Hop, Dancehall, Reggae, Trap, Afrobeats, Garage & House Use T&R maybe as background Image or use the image in there some where. use my attachments in the flyer also get an instagram twitter and soundcloud image and put follow @djslenderuk thank you

    Diseño de volantes Diseño gráfico Illustrator Photoshop Diseño con Photoshop
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    Verilog Altera Cyclone 5 maze game Finalizado left

    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit...chasing you and if he catches you, you are dead. The player's movement should not be pixel by pixel but rather, it should keep sliding until it hits the wall(boundary). The movement control should be done through the keys on the FPGA. The maze should have a fully functional non-flickering background, which should be easily be replaced. It should also have a start and game over screen. The work should have lots of comments, documentation, and test (.do) files so that it can be easily understood by a beginner. This should fully be implementable with the Cyclone 5 ters...

    Electrónica Ingeniería FPGA Microcontrolador Verilog / VHDL
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    Framer X Prototyping REACT Coding Finalizado left

    Working on a first prototype version of our Digital Real Estate Managment Assistant, we need some help on certain transactions a feature to build within our Framer X prototype. Therefore we are looking for a REACT developer familiar with the capabilities of Framer X to support us. We would consider an arrangement about 1 - 3 months one day a week. Requirements: - Knowing Framer X or keen to learn it - Min. 2-year experience of REACT development - Communicative in terms of active reporting - Familiar with Scrum Methodology using Asana, Jira, Github or keen to learn it - Fluently in English, as we will hold Skype meetings once a week - a holistic understanding of the possibilities within web development (nice to have) - python would be nice but nur necessary Most imp...

    HTML JavaScript Python React.js Web Development
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    Verilog board mini game Finalizado left

    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made -- not imported from a library etc. The ...quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made -- not imported from a library etc. The work should have lots of comments ,documentation and test (.do) files so that it can be easily understood by a beginner. it should work with a FPGA...

    Programación en C Electrónica FPGA Microcontrolador Verilog / VHDL
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    Design FPGA code for MPEG-ts Decoding Finalizado left

    I need an FPGA selected and hardware design created for decoding of an MPEG-Transport Stream parallel interface from a DVB-T demodulator. The FPGA needs to decode the transport stream and extract the video data as well as any other data contained in the Transport stream, the FPGA must then extract a selected individual pixel, and its colours are extracted in 8 bit form (8bits for each of RGB). This pixel data will be outputted to an LED. The FPGA will know which pixel to select after decoding the transport stream and receiving data from the transport stream to tell it which pixel to select.

    Arduino Electrónica FPGA Microcontrolador Verilog / VHDL
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    Build a 4 bit Multiplier VHDL code which works on FPGA Board Finalizado left

    Hey Guys, My Project description is given below. Please rea...Project description is given below. Please read carefully and if you already have this you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the multiplier. The A, B, Start and Reset inputs should be controlled by toggle switches on the DE10-Lite board. You must display the Done output on an LED and the result (product) as a three-digit decimal value on three seven segment displays on the FPGA board. You also need to sh...

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    Construction Finalizado left

    I need help with Sketchup. I need someone to be able to add the framer plug in to my file and also be able to come up with a list of materials needed for the construction project.

    Modelado 3D Renderización 3D AutoCAD Autodesk Revit Arquitectura
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    Custom FPGA Project Finalizado left

    This is a multi-part project for the Lattice MACHXO2-4000 LOGIC IC.

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    FPGA and DSP develper Finalizado left

    Looking for a developer to interface high speed TI DAC with virtex 7 FPGA. I am having DAC34H84 DAC and VC707 kit- and want to interface the same DAC with VC707 Hardware that i have is DAC34H84 and VC707

    Ingeniería eléctrica Electrónica FPGA Diseño PCB Verilog / VHDL
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    Hardware Design Finalizado left

    - schematic capturing; - PCB lay-outing; - production files generation, prototype bringing-up and troubleshooting; - transferring to production. Required experience: mixed circuitry hardware design, digital interfaces: USB, ADC (120MHz), analog circuitry: impedance matching, ADC, frequencies up to 100MHz, clocking and sync schemes, FPGA/MCU and peripherals. Job Type: Contract Location: GTA

    Diseño de circuitos Ingeniería eléctrica Electrónica Microcontrolador Diseño PCB
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