DDR4 ZynqUS+ Custom IP

Cerrado Publicado hace un año Pagado a la entrega
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I need a code in VHDL for a custom IP to communicate with the DDR4 MIG, it can be through a DMA block with FIFO over the AXI bus. Everything must be done on the PL side, and must have the basic functions of writing and reading a data at a memory address. The code will be tested on the ZCU104.

Verilog / VHDL FPGA

Nº del proyecto: #36377054

Sobre el proyecto

4 propuestas Proyecto remoto Activo hace 12 meses

4 freelancers están ofertando un promedio de $106 por este trabajo

hfbbaig

Hello, I have been working with FPGA systems for more than ten years. I have worked with DDRx MIGs and their AXI based shims. I believe I can deliver your work with high quality. Looking forward to your positive resp Más

$75 USD en 20 días
(1 comentario)
3.4
mamdouhellamie

Dear, I am an Electronics engineer holding a master degree in Digital Electronics. I have experience in VHDL in vivado design suite. I also teach the digital electronics lab where i supervise student projects in VHDL.

$20 USD en 7 días
(0 comentarios)
0.0
fourier54

I work on digital design for ASIC, I can perform what you are asking for. Please provide more details

$30 USD en 14 días
(0 comentarios)
0.0