Computer assignment

I need solution of the attached questions.

1. (24 points) Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the commentary, i.e.:

• a one clock cycle fetch

• a one clock cycle decode

• a four clock cycle execute

and a 40 instruction sequence:

• no pipelining would require _____ clock cycles:

• a scalar pipeline would require _____ clock cycles:

• a superscalar pipeline with two parallel units would require ______ clock cycles:

2. (30 points) Show the layout of the specified cache for a CPU that can address 512K words x 8 bits/word of memory. Give the layout of the cache words and the total number of cache words.

(Hint: Similar to Self-Assessment Question 6 and Discussion Topic 9)

6. What C++ variable type would you use to declare the following variables, which have the indicated initial values:

a. x = 2.366

b. y = 2

c. z = '2'

a) The cache holds 16K words x 8 bits/words of data and has the fully associative strategy

b) The cache holds 16K words x 8 bits/words of data and has the direct mapped strategy

c) The cache holds 16K words x 8 bits/words of data and has the two-way set-associative strategy

3. (3 points) Indicate with an X which of the following are RISC CPU characteristics that differentiate RISC from CISC.

____________ a) used in IBM 360 processors

____________ b) has a limited and simple instruction set

____________ c) uses pipelining

4. (10 points) Create a page translation table the meets the requirements of the virtual memory system shown below. Assume page (and frame) sizes of 5 with pages 0 through 3 in logical memory and frames 0 through 7 in physical memory.

Logical Memory Physical Memory

0

4 A

0

9

5

19

B

B

10

24

20

25

29

30

34

A

35

39

40

Page Frame

5. (20 points) Assume a computer system with 16K of memory, a Memory Management Unit with a page size of 2000, and the following page translation table (all numbers in hexadecimal):

Logical Address Physical Start

0000 10A00

2000 1F200

4000 2CC00

6000 22400

8000 30300

A000 41600

C000 81E00

E000 3F500

Note: All additions and subtractions should be done in hexadecimal

a. Indicate the physical memory location corresponding to logical address E600.

b. Indicate the logical address corresponding to physical memory location 30A51.

6. (3 points) List the hierarchy of memories with the fastest access time at the top.

7. (7 points) Match the descriptions below with the most appropriate memory management scheme (A through E). Answers may be used once, more than once, or not at all.

A. Fixed-partition multiprogramming

B. Single task system

C. Variable-partition multiprogramming

D. Virtual memory system with paging

E. Virtual memory system with segmentation

______________ a) contiguous allocation of memory in regions whose size cannot be varied

______________ b) contiguous allocation of memory where region size can be varied dynamically

______________ c) contiguous allocation of memory where holes are created as programs are moved in and out of memory

______________ d) programs are loaded into memory using a best-fit, first-fit, or largest-fit algorithm

______________ e) not capable of multitasking

______________ f) non-contiguous allocation of equal-sized blocks

______________ g) non-contiguous allocation of unequal-sized blocks

8. (12 points) Consider Poor Richard’s cache as describ

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