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$30 USD / hora
Bandera de EGYPT
beni suef, egypt
$30 USD / hora
Aquí son las 11:25 a. m.
Se unió el octubre 13, 2020
15 recomendaciones

Islam Muhammad S.

@IslamAdam998

 5,0 (43 comentarios)
6,1
6,1
67%
67%
$30 USD / hora
Bandera de EGYPT
beni suef, egypt
$30 USD / hora
96 %
Trabajos finalizados
73 %
Dentro del presupuesto
80 %
A tiempo
13 %
Tasa de recontratación

Digital IC Design Engineer (ASIC & FPGA)

I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL languages. I studied Nano-Electronics engineering bachelor's and interested in VLSI careers. I have experience with Vivado, ISE, SDK, Quartus, Design Compiler, IC Compiler and others. I have a special interest in CNN, AI, and autonomous applications and I have completed projects relating to fields both academic and industrial.
Freelancer Verilog / VHDL Designers Egypt
Ver todo Verilog / VHDL Designers en Egypt

Contacta Islam Muhammad S. sobre tu trabajo

Inicia sesión para comentar cualquier detalle por chat.

Portafolio

9674675
I have designed the tracking function for GNSS-SDR receiver. The implementation is based on a working C++ code tested on real-time data. For implementing the tracking function, I have designed PLL, DLL and FLL functions that are necessary in the design. Also, to compute complex functions used in the C++ code such as ArcTan, Log, complex numbers multiplication and division, Sin, and Cos, I used many Xilinx IPs that work together in a pipeline fusion. I have validated all functions used, and finished the design of the tracking function for industrial purposes. The code uses floating point representation for high accuracy computation. Yet, the design can be hardware accelerated to fixed-point representation to make the design faster and use less resources. The Verilog codes, and C++ codes are ready. Also, there is a full documentation for the project. If anyone is interested to buy my work or modify on it, just send me to make a deal.
GNSS-SDR Tracking Function for GNSS Receiver
I have designed the tracking function for GNSS-SDR receiver. The implementation is based on a working C++ code tested on real-time data. For implementing the tracking function, I have designed PLL, DLL and FLL functions that are necessary in the design. Also, to compute complex functions used in the C++ code such as ArcTan, Log, complex numbers multiplication and division, Sin, and Cos, I used many Xilinx IPs that work together in a pipeline fusion. I have validated all functions used, and finished the design of the tracking function for industrial purposes. The code uses floating point representation for high accuracy computation. Yet, the design can be hardware accelerated to fixed-point representation to make the design faster and use less resources. The Verilog codes, and C++ codes are ready. Also, there is a full documentation for the project. If anyone is interested to buy my work or modify on it, just send me to make a deal.
GNSS-SDR Tracking Function for GNSS Receiver
I have designed the tracking function for GNSS-SDR receiver. The implementation is based on a working C++ code tested on real-time data. For implementing the tracking function, I have designed PLL, DLL and FLL functions that are necessary in the design. Also, to compute complex functions used in the C++ code such as ArcTan, Log, complex numbers multiplication and division, Sin, and Cos, I used many Xilinx IPs that work together in a pipeline fusion. I have validated all functions used, and finished the design of the tracking function for industrial purposes. The code uses floating point representation for high accuracy computation. Yet, the design can be hardware accelerated to fixed-point representation to make the design faster and use less resources. The Verilog codes, and C++ codes are ready. Also, there is a full documentation for the project. If anyone is interested to buy my work or modify on it, just send me to make a deal.
GNSS-SDR Tracking Function for GNSS Receiver
I have designed the tracking function for GNSS-SDR receiver. The implementation is based on a working C++ code tested on real-time data. For implementing the tracking function, I have designed PLL, DLL and FLL functions that are necessary in the design. Also, to compute complex functions used in the C++ code such as ArcTan, Log, complex numbers multiplication and division, Sin, and Cos, I used many Xilinx IPs that work together in a pipeline fusion. I have validated all functions used, and finished the design of the tracking function for industrial purposes. The code uses floating point representation for high accuracy computation. Yet, the design can be hardware accelerated to fixed-point representation to make the design faster and use less resources. The Verilog codes, and C++ codes are ready. Also, there is a full documentation for the project. If anyone is interested to buy my work or modify on it, just send me to make a deal.
GNSS-SDR Tracking Function for GNSS Receiver
9033964
This is the implementation of PCIe core on Zynq Ultrascale FPGA. The core utilized AXI4 protocol and supports a high data rate of up to 1.6 GB/S
PCIe core with 1600 MB/s data rate
This is the implementation of PCIe core on Zynq Ultrascale FPGA. The core utilized AXI4 protocol and supports a high data rate of up to 1.6 GB/S
PCIe core with 1600 MB/s data rate
This is the implementation of PCIe core on Zynq Ultrascale FPGA. The core utilized AXI4 protocol and supports a high data rate of up to 1.6 GB/S
PCIe core with 1600 MB/s data rate
9031709
This is a design for Manchester encoding and decoding using Vivado and Verilog language. It is tested OK.
Manchester encoding and decoding
This is a design for Manchester encoding and decoding using Vivado and Verilog language. It is tested OK.
Manchester encoding and decoding
9028084
This is a C code for AES 128 Encryption Decryption synthesized and tested on Vivado HLS.
AES 128 Encryption Decryption
This is a C code for AES 128 Encryption Decryption synthesized and tested on Vivado HLS.
AES 128 Encryption Decryption
This is a C code for AES 128 Encryption Decryption synthesized and tested on Vivado HLS.
AES 128 Encryption Decryption
8888862
This is a screenshot from the SHA256 mining algorithm which is a famous algorithm used for Ethereum and Bitcoin mining. I did the RTL and generated the bitstream for it.
SHA256 mining Algorithm
This is a screenshot from the SHA256 mining algorithm which is a famous algorithm used for Ethereum and Bitcoin mining. I did the RTL and generated the bitstream for it.
SHA256 mining Algorithm
8840363
UART for serial data transfer to PC.
UART
9674675
I have designed the tracking function for GNSS-SDR receiver. The implementation is based on a working C++ code tested on real-time data. For implementing the tracking function, I have designed PLL, DLL and FLL functions that are necessary in the design. Also, to compute complex functions used in the C++ code such as ArcTan, Log, complex numbers multiplication and division, Sin, and Cos, I used many Xilinx IPs that work together in a pipeline fusion. I have validated all functions used, and finished the design of the tracking function for industrial purposes. The code uses floating point representation for high accuracy computation. Yet, the design can be hardware accelerated to fixed-point representation to make the design faster and use less resources. The Verilog codes, and C++ codes are ready. Also, there is a full documentation for the project. If anyone is interested to buy my work or modify on it, just send me to make a deal.
GNSS-SDR Tracking Function for GNSS Receiver
I have designed the tracking function for GNSS-SDR receiver. The implementation is based on a working C++ code tested on real-time data. For implementing the tracking function, I have designed PLL, DLL and FLL functions that are necessary in the design. Also, to compute complex functions used in the C++ code such as ArcTan, Log, complex numbers multiplication and division, Sin, and Cos, I used many Xilinx IPs that work together in a pipeline fusion. I have validated all functions used, and finished the design of the tracking function for industrial purposes. The code uses floating point representation for high accuracy computation. Yet, the design can be hardware accelerated to fixed-point representation to make the design faster and use less resources. The Verilog codes, and C++ codes are ready. Also, there is a full documentation for the project. If anyone is interested to buy my work or modify on it, just send me to make a deal.
GNSS-SDR Tracking Function for GNSS Receiver
I have designed the tracking function for GNSS-SDR receiver. The implementation is based on a working C++ code tested on real-time data. For implementing the tracking function, I have designed PLL, DLL and FLL functions that are necessary in the design. Also, to compute complex functions used in the C++ code such as ArcTan, Log, complex numbers multiplication and division, Sin, and Cos, I used many Xilinx IPs that work together in a pipeline fusion. I have validated all functions used, and finished the design of the tracking function for industrial purposes. The code uses floating point representation for high accuracy computation. Yet, the design can be hardware accelerated to fixed-point representation to make the design faster and use less resources. The Verilog codes, and C++ codes are ready. Also, there is a full documentation for the project. If anyone is interested to buy my work or modify on it, just send me to make a deal.
GNSS-SDR Tracking Function for GNSS Receiver
I have designed the tracking function for GNSS-SDR receiver. The implementation is based on a working C++ code tested on real-time data. For implementing the tracking function, I have designed PLL, DLL and FLL functions that are necessary in the design. Also, to compute complex functions used in the C++ code such as ArcTan, Log, complex numbers multiplication and division, Sin, and Cos, I used many Xilinx IPs that work together in a pipeline fusion. I have validated all functions used, and finished the design of the tracking function for industrial purposes. The code uses floating point representation for high accuracy computation. Yet, the design can be hardware accelerated to fixed-point representation to make the design faster and use less resources. The Verilog codes, and C++ codes are ready. Also, there is a full documentation for the project. If anyone is interested to buy my work or modify on it, just send me to make a deal.
GNSS-SDR Tracking Function for GNSS Receiver
9033964
This is the implementation of PCIe core on Zynq Ultrascale FPGA. The core utilized AXI4 protocol and supports a high data rate of up to 1.6 GB/S
PCIe core with 1600 MB/s data rate
This is the implementation of PCIe core on Zynq Ultrascale FPGA. The core utilized AXI4 protocol and supports a high data rate of up to 1.6 GB/S
PCIe core with 1600 MB/s data rate
This is the implementation of PCIe core on Zynq Ultrascale FPGA. The core utilized AXI4 protocol and supports a high data rate of up to 1.6 GB/S
PCIe core with 1600 MB/s data rate
9031709
This is a design for Manchester encoding and decoding using Vivado and Verilog language. It is tested OK.
Manchester encoding and decoding
This is a design for Manchester encoding and decoding using Vivado and Verilog language. It is tested OK.
Manchester encoding and decoding
9028084
This is a C code for AES 128 Encryption Decryption synthesized and tested on Vivado HLS.
AES 128 Encryption Decryption
This is a C code for AES 128 Encryption Decryption synthesized and tested on Vivado HLS.
AES 128 Encryption Decryption
This is a C code for AES 128 Encryption Decryption synthesized and tested on Vivado HLS.
AES 128 Encryption Decryption
8888862
This is a screenshot from the SHA256 mining algorithm which is a famous algorithm used for Ethereum and Bitcoin mining. I did the RTL and generated the bitstream for it.
SHA256 mining Algorithm
This is a screenshot from the SHA256 mining algorithm which is a famous algorithm used for Ethereum and Bitcoin mining. I did the RTL and generated the bitstream for it.
SHA256 mining Algorithm
8840363
UART for serial data transfer to PC.
UART

Comentarios

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5,0
$1.778,00 USD
Stage 1 cryptocurrency FPGA and ASIC core and multi-core design and optimisation
Islam has done an incredible job. He has over delivered which is a wonderful breath of fresh air! He is very well versed in the design process and displays immense skills! I will definitely continue to use him on other projects in the future and can recommend him without any reservations.
Verilog / VHDL
FPGA
Digital Electronics
ASIC
+1 más
A
Bandera de Arie Z.
@AriZed
•
hace 2 años
4,8
$1.200,00 USD
Project for Islam Muhammad S. -- 2
Islam delivered and it's very knowledgable
Verilog / VHDL
FPGA
Digital Electronics
ASIC
+1 más
A
Bandera de Arie Z.
@AriZed
•
hace 2 años
5,0
$320,00 USD
Project 33858018 has been deleted
He is true professional and very nice person. Highly recommended for future endeavors.
S
Closed User
@shahidlatifawan1
•
hace 2 años
5,0
$167,00 USD
Verilog code on FPGA
Nice work I recommend it
C Programming
Engineering
Verilog / VHDL
Software Development
FPGA
M
Bandera de Mo T.
@mohT2030
•
hace 2 años
5,0
€1.533,00 EUR
FPGA Game on Intel ARM Processor
Has the knowledge needed
Verilog / VHDL
FPGA
Digital Electronics
ASIC
+1 más
M
Bandera de Mohamed Samir M.
@MedSamir
•
hace 2 años

Contacta Islam Muhammad S. sobre tu trabajo

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Verificaciones

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Certificaciones

preferredfreelancer-1.png Preferred Freelancer Program SLA 1 92%

Principales habilidades

Verilog / VHDL 45
FPGA 39
ASIC 20
Digital Electronics 19
Digital ASIC Coding 19

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