Verilog code for Turing machine

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I want to design a verilog code for turing machine under EDAplayground at link [login to view URL]

I have already made code in C  ( c code file is attached herewith) and it is working but I need to make it in verilog in the said online verilog compiler [login to view URL]

description for the working of Turing machine is as given below:

We want to output “ABC”

The code would be

i0 65 // load the register 0 with 65 which is ASCII “A” (hex 41)

i1 3 // load the register 1 with value 3

[x // set a Startmarker for a loop

oO // output the content of register 0

+0 // increment register 0

]1 // decrement register 1. If the result is not zero go back to Startmarker

Let’s say we replace the symbolic code with hex-numbers:

i = A // example A5 65 => load Register #5 with ASCII "A"

o = F

+ = B // example B5 => increment Register #5 (which get s "B")

[ = C // example C0 sets a start marker (label) for a loop

- = E

] = D

The code sequence would look like A0 41 A1 03 C0 F0 B0 D1

two digits after AO that is 41 will come out as result 44

that means

for 41 result will be 44

for 51 result will be 54

I conclude that result will be 3 digits higher any input.

please make in [login to view URL]

and send me both text files for [login to view URL] and [login to view URL] and also share with me the complete program from compiler [login to view URL]

//C program for turing machine short

#include<stdio.h>

#include <stdlib.h>

#include <string.h>

#include <math.h>

int main() {

char string[1000]="A041A103C0F0B0D1";

char sub1[1];

char sub2[2];

char sub3[2];

char A[1];

char C[1];

char F[1];

char B[1];

char D[1];

int reg0;

int reg1;

int a1=0;

char b1[1];

char b2[1];

int l;

l=strlen(string);

int l1=0;

int l2=0;

int l3=1;

int c=0;

int i=0;

int j=0;

int k=0;

int k1=0;

int p0;

int p1;

int p2;

int output;

//main while loop

while (i<=(l+20))

{

j=0;

p0=i+1;

while(j<=0)

{

sub1[j] = string[p0+j-1];

//selection of the command word:A,F,B,C,E,D

//for first case{A041} po=1,j=0,i=0 and second case{A103} po=1,j=0,i=5

j++;

}

//in main loop;

int result;

result = strcmp(sub1, "A" );

switch(result)

{

case 0:

//printf("Case 0 started\n");

k=0;

p1=i+2;

while (k<=l2)

{

sub2[k] = string[p1+k-1];

k++;

}

//check sub2 is '0' or '1' or say for first case{A041} or second case{A103}

if(sub2==a1)

{

b1[1]=sub2[1];

}

else

{

b2[1]=sub2[1];

}

k1=0;//counter for data word

p2=i+2;

while (k1<=1)// while loop to get data to be processed

{

sub3[k1] = string[p2+k1];

k1++;

}

reg1 = reg0;

if(atoi(sub2)==a1)

{

//sub3 string is converted to numeric and saved in reg0 or reg1

reg0=atoi(sub3);

//printf("reg0 is = %d\n",reg0);

}

//else

//{

//reg1=atoi(sub3);

//printf("reg1 is = %d\n",reg1);

//}

int pA=p0;// pointer poistion for char A

break;

case 2:// case statement for char C

//printf("Case 2 started\n");

p0=9;

//printf("sub1 is = %s\n",sub1);

break;

case 5:// case statement for char F

//printf("Case 5 started\n");

reg0=reg0+1;

//printf("reg0 is = %d\n", reg0);

break;

case 1:// case staement for char B

//printf("Case 1 started\n");

reg1=reg1-1;

//printf("reg1 is = %d\n", reg1);

break;

case 3:// case staement for char D

//printf("Case 3 started\n");

if(reg1!=0)

{

p0=9;

//printf("i= %d\n",p0+1);

}

else

{

p0=l+21;

}

break;

// operator doesn't match any case constant +, -, *, /

//default:

//printf("Turing machine reached to end of text\n");

}

//end of switch case

//comparing result pf all characters ('A','B','C','D','F') with result of char 'A' and select increment in p0

if(result==0)

{

p0=p0+4;

}

else

{

p0=p0+2;

}

i=p0-1;

}

//printf("At i = %d the output reg 1 is = %d\n",i, reg0);

printf("The output of register '0' is = %d\n",reg0);

return 0;

}

Verilog / VHDL Programación en C++ Programación en C FPGA Assembler

Nº del proyecto: #25674654

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kundanvaghela

i got same project today just before half hour, i have 2+ year experience in design and verification, i have done 25+ project in verilog/VHDL, i will done your project perfectly and on time, i will provide support a Más

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shwetapd95

Hi, your task can be done with the Vivado HLS tool which helps to convert C into synthesized Verilog code. I have recently completed a course of Vivado HLS. I can help with your project. I have more than 3 years of tot Más

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ssoundarya228f

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gauravrocks198

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sayantanghosh290

I have some experience in Verilog,C and VHDL. I have worked on a lot of courses during my coursework. Willing to take up projects to expand my knowledge and experience.

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ksv1517lata

nice problem, it can be done in verilog I can quickly convert your code in verilog module along with a testbench for simulation.

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