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Filter bank Simulink and VHDL implementation

£20-250 GBP

Cerrado
Publicado hace más de 5 años

£20-250 GBP

Pagado a la entrega
My aim of this work is to see how it would be done from a different point of view. What I would like to be done is: * Check the Simulink model to see if that's done correctly. * Finish minimum resource version in filter bank Simulink model (just add memory and switch between memory in each cycle and do DFT). * Implement the minimum resource filter bank in VHDL in the simplest possible way. It can be done on HDL designer or Simulink VIVADO Signal Generator. * Create a word file with short explanations how VHDL model works and add guidelines what algorithm was used to implement DFT. * Do a bit-true simulation in order to confirm that VHDL model works the same as the Simulink minimum resource version. Filter bank specification is given in [login to view URL] file Number of users: 4 Sampling frequency: 16kHz
ID del proyecto: 18292582

Información sobre el proyecto

4 propuestas
Proyecto remoto
Activo hace 5 años

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4 freelancers están ofertando un promedio de £167 GBP por este trabajo
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Dear sir I have more than 10 years experience in digital design using FPGA please message me so that we can discuss
£200 GBP en 3 días
4,9 (420 comentarios)
7,8
7,8
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I have well experienced in doing such kind of jobs...........................................................................................
£150 GBP en 3 días
4,9 (48 comentarios)
5,6
5,6
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I am expert who understands the value of time. I pride myself in my attention to detail. I am very hard working and aim to deliver in less time than quoted. I want to make you, my employer happy without changing my bid or playing games. If you are looking for a true Freelancer, I am the Right person for you. I am available almost 24-7 and am very responsive. I feel proud that I am a trusted Freelancer who pleases almost every single client. You can rest assure, your work will be delivered well in advance of others, with passion and accuracy. I guarantee you instant communication & responses when you need me. Why choose me? I think every client is the reason for my success. I only take projects which I am sure I can do quickly and at my FIRST BID. I promise to deliver 100% Satisfaction.I have more than 5 year of experience in Electrical Engineering, Engineering, FPGA, Matlab and Mathematica, Verilog / VHDL. Please ping me for more discussion.
£150 GBP en 3 días
5,0 (23 comentarios)
5,1
5,1
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Dear sir, I have experience in both simulink and Hdl . You will your solution in both Matlab and modelsim.
£166 GBP en 3 días
0,0 (0 comentarios)
0,0
0,0

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Bandera de UNITED KINGDOM
London, United Kingdom
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Miembro desde dic 4, 2018

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