fpga implementation of turbo decoder using QPP interleaver for wireless communications

I am a hardware designer in Silicon Valley, California USA specializing in the developing hardware for security firewall ASICs and FPGAs. Projects that i have completed include hardware schedulers, parsers, packet inspection engines and encryption modules. I am well versed in the whole development process from writing synthesizable hardware code, closing timing and placement on FPGA or ASIC. Confortable with Xilinx compiler and tools. Have used FPGA from the Virtex, Zynq and Ultrascale family devices. Therefore, i am well suited to help you on this project. Besides that, i am a good communicator and strive to deliver on time accurately.

Great experience in FPGAs. Work with communication and information transfer systems. Work with digital signal processing

hello Myself Akriti electronics and communication engineering Student at NIT Jalandhar with 6 month experience in VHDL and system designing. But i am comfortable with VHDL using xilinx not verilog.